A typical computer processing system (such as a general-purpose CPU, digital-signal processor (“DSP”) MCU, MPU, FPGA, ASIC, ASSP, or any other type of computer processor) includes a core processor (“core”) and a plurality of special-purpose modules in communication therewith. The core executes DSP-related and other processing functions, and the modules may be random-access or other memories, direct-memory-access (“DMA”) devices, co-processors, input/output handlers, timers, or any other similar circuitry. To activate a module to perform an operation (referred to herein as an “event”), the core processor receives a request to initiate the event and sends an initiation message (referred to herein as a “trigger”) to the module via, for example, use of a software interrupt. The core may thus exchange data, address, and/or control signals with one or more of the modules to, for example, send data to or load data from a memory module.
Often, however, one module may send data (or other information) directly to another module without the need for the information to pass through a processor or “core.” For example, a DMA-capable device (which facilitates direct access to memory without the involvement of the core) may interact directly with a memory module or other DMA-capable device. The core, however, is still needed to schedule and trigger initiation of the event, thus creating overhead (e.g., interrupt handling and service routine overhead) in the core and reducing the performance thereof. At most, a DMA controller may relieve the core of triggering certain DMA events by “chaining” the events (i.e., completion of a first DMA event triggers a second one). This DMA chaining is, however, limited to only certain kinds of DMA events and, moreover, cannot be used for other module types (e.g., non-DMA modules). A need therefore exists for a robust, programmable system and method for relieving the core processor of a wide variety of triggering responsibility.